1. Field of the Invention
This invention relates to a phase locked loop circuit (hereinafter referred to as PLL circuit), and, more particularly, to improvement in the characteristic thereof.
2. Description of the Related Art
Heretofore analog type PLL circuits have been often employed in devices of varied kinds. FIG. 1 of the accompanying drawings is a block diagram showing, by way of example, the arrangement of the conventional PLL circuit. The illustration includes a monostable multivibrator 1 (hereinafter referred to as MM); a phase comparator 2 (hereinafter referred to as PD) which is capable of producing an output at three different levels including a high level, a medium level and a low level; a voltage controlled oscillator 3 (hereinafter referred to as VCO); a frequency divider 4; and a terminal 5 which is arranged to receive an incoming rectangular wave signal. FIG. 2 is a timing chart showing the waveforms of signals (a) to (d) obtained at various prints in the circuit of FIG. 1. Referring to FIG. 2, the conventional PLL circuit operates as follows: The signal (a), which is of a rectangular waveform, comes from the outside and is applied to the terminal 5. The incoming signal (a) is applied to the MM 1. The MM 1 then supplies the signal (b) of pulse width TW to the PD 2. The PD 2 receives another comparison signal input, which is a signal (c) produced from the frequency divider 4 by down counting the oscillation output of the VCO 3 down to 1/n. The PD 2 compares the phases of these signals (b) and (c) and produces the signal (d). The signal (d) is supplied directly to the VCO 3. The VCO 3 oscillates at three different frequencies FL, FM and FH according to the three different output levels VL, VM and VH of the PD 2. The oscillation output of the VCO 3 is supplied to the frequency divider 4 to be frequency divided into 1/n. The frequency divided output of the VCO 3 is supplied to the comparison input terminal of the PD 2. A closed loop is thus formed.
The conventional PLL is characterized by a quck responsivity derived from includion of no low-pass filter within the above-stated closed loop. Further details of the arrangement and the advantages of this prior art PLL circuit are as mentioned in Japanese Laid-Open Patent Application No. SHO 60-84017 and U.S. Pat. application Ser. No. 659,717, filed Oct. 11, 1984, now U.S. Pat. No. 4,626,797, in common assignment herewith, and are, therefore omitted from the following description.
Generally, for obtaining a high speed responsivity and a high degree of stability of the PLL circuit of the above-stated kind, the signal (b), which is the reference input to the PD 2 and to be used for setting the period of control over the VCO 3, cannot be allowed to have a large pulse width TW for the incoming signal. Assuming that the frequency of the incoming signal is fT, 1/fT sec is 63,556 .mu.s in the event of fT=15,734 KHz. The reason for that the pulse width TW cannot be large is as follows: With the output signal (D) of the PD 2 arranged to be supplied directly to the VCO 3 and with the VCO 3 arranged to generate three different frequencies FL, FM and FH, the period of the oscillation frequency FM of the VCO 3, which is the free-running period of the VCO 3, inevitably becomes long. During this free-running period, however, the output frequency sensitivity reacts to the temperature resulting from the temperature characteristic of the VCO 3 at a level VM. This adverse effect of temperature makes the frequency FM instable. The instability of the control input has not only increased the instability of the closed loop of the PLL circuit but also narrowed the phase-lock pull-in range of the conventional PLL circuit.